Modified : jan. 31st 2008

Dual GATED SLEW
En français
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Description

This is an utility module that may find some use to create gated portamento effects or other slew limiting effect. It is a dual module and each submodule has its own  SLEW RATE potentiometer. A GATE input jack makes it possible to control the slew function (only in the LOG mode though) : GATE OFF --> No slew, GATE ON--> Slew activated. The default status (no jack inserted in the GATE input) is Slew activated. The slew status is shown by a LED. Furthermore two toggle switches are available.
The first one is a three state switch which sets the active slew phase : The second switch is a two state switch which defines the slew function :

  1. slew active on rising edge only
  2. slew active on both rising and falling edges
  3. slew active on falling edge only
  1. linear slew (no gated mode)
  2. logarithmic slew (gated mode)

Schematic

The principle of this circuit is quite simple.
LOG mode :
In the LOG mode, U1a acts as a simple voltage follower (pin 6 is fedback to pin 2), it buffers the input signal.  Let's consider that SW1 is in it's middle position, in such a case the voltage at the output of U1a (pin 6) is going to either charge C3 (if this voltage is higher than that at C3) or dischage C3 (if this voltage is lower than that at C3) through R4 and P1. The greater the value of P1, the longest the charging/discharging time. Then U1b acts as a simple voltage follower and buffers the voltage at C3 to the output.
If we toggle SW1 on the Up lug, then diode D2 bypasses the SLEW RATE potentiometer P1, in such a case the discharging rate of C3 will only depends on R4 (10 ohms) and thus is very fast, while the charging rate still depends on P1. Now if we toggle SW1 on the Down lug, now it's diode D1 that bypasses P1 and therefore it's the charging rate of C3 that becomes very fast and the discharging rate still depends on P1.

GATED mode :
Now let's consider the part played by the FET transistor Q1, in this configuration it acts as a bypass switch for P1 when a positive voltage is applied to the grid of Q1 (the drain-source resistance drops to 50 to 60 ohms). When a negative voltage (which is the default) is applied to the grid of Q1, the drain-source resistance rises to few megohms and P1 becomes active. When no jack is plugged in the GATE input, R11 is connected to the input of the comparator built with U2, this positive voltage is higher than the reference voltage set by the the voltage divider made with R8 and R9. Therefore the output of U1 is negative and opens the FET switch Q1. At the same time this voltage sets the grid of Q2 to 0V (D4 blocks the negative voltage), the drain-source resistance of Q2 is nearly infinite and the current circulating through R10 feeds LD1 which in turns emit a RED light.  If a jack is connected to the GATE input and the GATE voltage is 0V, the comparator switches and a positive voltage appears on its output. This positive voltage makes Q1 and Q2 conductive that is their drain-source resistance becomes negligible. As consequence P1 and  LD1 are bypassed, the SLEW rate becomes very fast (few ms) and the LED is dark. If a positive (>1.5V) voltage is applied at the GATE input, the comparator toggles and a negative voltage is applied to the grids of Q1 and Q2, P1 becomes active and the LED brightens.

LIN mode :
In this mode U1 is no longer a voltage follower of the input voltage but is also controlled by the output voltage of the modules (output of U1b is fed back to the inverting input of U1b). In such a configuration the charging/discharging current of C3 is no longer depending on the instantaneous charge of C3 but is maintained constant. Because this current remains constant the charging/discharging curve of C3 remains linear. However in this feedback loop the Q1 FET transistor will no longer behave as simple switch, that's why in the linear mode the switch SW2-2 disconnects Q1.

Printed Circuit Board and Component Layout
PCB design
Layout






 Download the schematic as a PDF file 
Download the PCB as a PDF file 

WARNING ! The document is formatted to be printed directly on a mylar for photo-etching or a "press & peel" paper. Make sure that when the printed face of mylar is in contact with the copper side of the PCB, the lettering can be read normally.


List of parts and building instructions
reference
 value
 number
U1,U4
 TL072
 2
U2,U3
 TL071 (don't use a 741 it wouldn't work!)
 2
Q2,Q4
 BS170
 2
Q1,Q3
 BF245
 2
D1,D2,D3,D4,D5,D6,D7,D8
 1N4148
 8
R1,R2,R4,R13,R21
 10 ohms
 5
R5,R14
 470 ohms
 2
R10,R19
 1k
 2
R9,R11,R18,R20
 12k
 4
R6,R8,R15,R17 120k
 4
R3,R14
 1M
 2
R7,R16
 2.2M
 2
C4,C5,C7,C8
 100nF
 4
C3,C6
 680nF or 1µF polyester multi layer
 2
C1,C2,C9
 22µF/25V electro.
 3
LD1,LD2
 red LED
 2
P1,P2
 1M log potentiometer
 2
Jk1,Jk2,Jk3,Jk4,Jk5,Jk6 6.5 mm jack socket
 6
SW1,SW3
 3 positions 1 circuit (ON OFF ON) toggle switch
 2
SW2,SW4
 2 positions 2 circuits toggle switch
 2

Wiring




Front plate
Panel design


 Download the silkscreen mask as a PDF file 


Download the silkscreen mask as a  JPEG file 



Trimming
This circuit requires no setting or trimming. It must work right away.


References
Information and datasheet for BF245
Information and datasheet for BS170  
The DIY builders' gallery
Here are the photographs of the yusynth ARP modules built by other synth geeks around the world.
Thank you  guys for sending me these nice photos.



Name  : Patrick
Pseudo : Baronrouge
Modular project: JHC live lab
Location Toulon, France
Web site : http://myspace.com/patjhc

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