Modified : dec. 13th. 2008

CLOCK DIVIDER

En français
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Description


This module is meant to be a complement of step sequencers or to be used to trigger events at regular beats. It provides a way of clocking up to three step sequencers at various rates from a single external master clock, the master clock rate can be divided by 1 (unchanged rate), 2, 3, 4, 5, 6, 7 or 8 independently on the three dividers.

The three dividers can be clocked by the same clock signal on input IN #1, but a different master clock can be used for the second and third dividers by plugging it in the input IN #2 & 3.

The divided clock signals are available at outputs OUT #1, OUT #2 and OUT #3, and are visualized with LEDs.

A RESET input is provided to synchronize the dividers. Note that the outputs are all shaped to the same pulse width as that of the external clock.

Example : one master clock, STEP #1 = 1/2, STEP #2 = 1/3, SETP #3 = 1/5



Schematic



How it works :
Channel #1:
The input signal is applied to a Schmitt trigger (Q1-Q2) which converts the clock signals to a proper logical level (0V or 15V). Q1-Q2 are connected as a classical discrete Schmitt trigger. R3,R4 are large value resistors that insure a high input impedance. Diode D1 prevents the input transistor from negative voltages. The logical level available at the collector of Q1 is applied to the CLOCK pin (pin 14) of a classical decade counter CMOS IC (4017). The 0 count pin of the 4017 (pin 3) is sent to one input (D5) of a discrete AND gate formed by D4, D5 and R9.  The second input (D4) of this AND gate receives the clock  signal from the collector of Q2. This way the output is shaped to the same pulse width as the clock input. Q3 acts as a buffer and the output signal is available through R17. LD1 show the status of the output. With the values shown on the schematics the logical ON level is 10V. If a 5V level is preferred, then use the optional zener diode Z1 (5.1V), the PCB is provided with pads for soldering the optional zener. The other counting pins of the 4017 (1 to 8) are sent to a eight position rotary switch which common pin is connected to one input (D3) of a discrete OR gate formed by D2, D3 and R8. This OR gate is connected to the RESET pin (pin 15) of the 4017 and resets the decade counter to 0 when the number of steps selected with the rorary switch has been reached. The second input (D2) of the OR gate is connected to a sub-circuit built with Q10 and Q11. This sub-circuit makes it possible to reset the counter to 0 with an external RESET signal. The external reset signal is applied to the base of Q10. The capacitor C10, differentiates the logical level at the collector of Q10 and the positive part of the differentiated signal is converted to a 1 ms pulse by Q11. Then this pulse is sent to D2.

The maximum current draw of this module is 20mA at +15V.

Printed Circuit Board and Component Layout

PCB design


Layout





Download the schematic as a PDF file 
Download the PCB as a PDF file 

WARNING ! The document is formatted to be printed directly on a mylar for photo-etching or a "press & peel" paper. Make sure that when the printed face of mylar is in contact with the copper side of the PCB, the lettering can be read normally.
NOTE : do not forget to solder the three little straps at pin 14 of U1,U2,U3; if you wish that the OUTPUTS operates at 5V rather than 10V then do not forget to solder the zener diodes Z1,Z2 and Z3.

Part list and building instructions

reference
value
number
U1,U2,U3
4017 CMOS decade counter
3
Q1.....Q11
BC547
11
D1.....D16
1N4148
16
Z1....Z3
optional 5V zener diodes (see text)
3
R1,R2
10 ohm 5% 2
R5,R12,R17,R24,R29,R36 220 ohm 5% 6
R8,R14,R20,R26,R32,R38 1K 5%
6
R13,R25,R37
1.5K 5% 3
R10,R22,R34 4.7K 5% 3
R41 10K 5%
1
R6,R7,R9,R18,R19,R21,R30,R31,R33,R42
R43
22K 5% 11
R39 100K 5%
1
R11,R23,R35 220K 5% 3
R3,R15,R27,R40 1M 5% 4
R4,R16,R28
1.2M 5% 3
C6
1nF to 2.2nF polyester film 1
C3,C4,C5
100nF multilayer ceramic
3
C1,C2
22µF/25V electro.
2
LD1,LD2,LD3
red LED
3
Jk1...Jk6
6.5 mm jack socket
6

Wiring



Front plate
Panel design
Download the silkscreen mask as a PDF file 
Download the silkscreen mask as a  JPEG file 



Trimming


This circuit requires no setting or trimming. It must work right away.

The DIY builders' gallery
Here are the photographs of the yusynth Clock Divider modules built by other synth geeks around the world.
Thank you  guys for sending me these nice photos.




Name :
Pseudo : Etaoin
Modular project : Casia MS01
Location : Utrecht, Netherlands
Website : www.casia.org/modular
Name : David Wood
Pseudo : Skrog
Modular project : Skrog Productions
Location : Galashiels , Scotland

Website : www.myspace.com/skrogproductions
Name : Frédéric Monti
Pseudo : Zarko
Modular project :
Location : Gardanne, France
Website :




Name : Steven Brenner
Pseudo :
Modular project :
Location : Waterloo, Ontario, Canada
Website :


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