Update : oct 28th, 2008

Envelope generator

ADSR
En français
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Description

The ADSR module provides a control voltage that makes possible shaping the envelope of a continuous sound. It is mainly used to control the gain of a VCA module or drive the cut off frequency of a VCF module. As usual it is not restricted to these two obvious applications and can be extended to the control of many others modules.
This module has a GATE input. The GATE signal determines the start and duration of the envelope signal. Four parameters can be set using potentiometers :

  • Attack duration : 1ms to 10s
  • Decay duration : 1ms to 10s
  • Sustain level : 0 to 10V
  • Release duration : 1ms to 10s

The direct ADSR signal is available on one output within 0 to 10V range and the inverted ADSR signal is available on a second output within 0 to -10V range.

A push button is available to manually generate a direct GATE signal. The intensity of the output signal can be visualised by means of a simple LED.

The power draw of this module is rather low : 10mA +15V rail, 3.6 mA -15V rail.

The heart of this circuit is based on an original idea by Jonathan Jacky (1980, see references at the end of this page).

Schematic

The schematic of this module is rather simple and uses very common components. The core of the schematic is based on an original idea by Jonathan Jacky  that was published in Electronics ("Two-chip generator shapes synthesizer's sounds" Electronics #11, September 1980 : 137-138). This core has inspired other DIYers (Tom G.-EFM, René Schmitz  ).

Three transistors (Q1 to Q3, BC547C) are used to process the GATE signal. D1 protects the circuit from negative voltages. Diodes D2 to D4 are used to dispatch the charge and discharge current of the timing capacity C4 (10µF/35V tantalum) through the potentiometers P1,P2 & P4. The 7555 chip (U1) is wired as a monostable timer. The two OPAs of the TL072 chip (U2) are used as a simple voltage follower and a voltage inverter, respectively. Next, transistor Q4 drives the control LED.

How does it work ?
  • GATE signal is off (0V)

The base of Q1 is at 0V et Q1 is blocked. The base of Q2 is at Vrail/2 and Q2 is conducting. Thus, pin 4 of the U1 is at 0V and maintains the timer in a quiet stage. Capacitor C4 is discharged and the output level is 0V. 
  • GATE signal is on (>3V)

When a gate signal occurs (>3V), Q1 comes to a conduction state, the base of Q2 comes to 0V and  Q2 is blocked. Thus pin 4 of U1 is at +Vrail (15V), at the same time a brief pulse is generated by C3 at the base of Q3, the latter becomes conductive for a few hundredth of second bringing pin 2 (trigger) of U1 to 0V for a brief time. These events trigger the timer. Pin 3 (out) of U1 reaches 15V  and capacitor is being charged through D2 and P1 whose value sets the ATTACK duration.
The voltage at C4 is monitored by pin 6 (threshold) of U1. When this value reaches 2/3 of Vrail that is 10V, the timer toggles, pin 3 goes to 0Vstopping the charging of C4. Then C4 start discharging itself through D3, R12 and P2 which value sets the DECAY speed, to eventually reach the voltage value set by the voltage divider P3-R10. This divider is calculated to provide a SUSTAIN voltage ranging from 0V to 10V. This value is held as long as the gate signal is up.
  • GATE signal returns to 0V  (Porte/Gate : 0 V)

The base of Q1 returns to 0V and Q1 is blocked. The base of Q2 is at Vrail/2 and Q2 comes to a conduction state. C4 starts discharging through D4, R19 and P4. The value of P4 sets the discharge speed that is the RELEASE duration. Pin 4 of the 7555 is set to 0V and switches the 7555 timer to a quiet state.

Printed circuit board and component layout
PCB design



 Component  layout




 Download the schematic as a PDF file
Download the PCB as PDF file
Download the component layout as a PDF file

Components and building guide
reference
 value
 quantity
U1
 7555 (CMOS version of the NE555)
 1
U2
 TL072
 1
Q1, Q2, Q3, Q4
 BC547C or equivalent (mind the pinout !)
 4
D1,D2,D3,D4
 1N4148
 4
R1,R2
 10 ohms
 2
R11,R12,R13
 100 ohms
 3
R4,R16,R20
 1K
 4
R10
 2.2K (adjust for the best compromise: LD1 glow versus current consumption)
 1
R14**
 4.7K (value to adjust to reduce any "Glitch")
 1
R17,R21
 10K
 2
R6,R7,R8,R9,R10
 22K
 5
R15,R19
 100K
 2
R5
 270K
 1
P1,P2,P4
 1M log
 3
P3
 10k lin
 1
C3,C5
 10n
 2
C6,C7,C8
 100nF ceramic or polyester
 3
C1,C2
 22µF 35V polarised 2
C4
 10µF 35V tantalum
 1
LD1
 LED, low current
 1
JK1,JK2,JK3
 female jack socket
 3
SW1
 push button (push to make)
 1
R3 is missing...
Wiring


Front panel
Panel design


 Silkscreening


 Download the silkscreen mask as a PDF file

Download the silkscreen mask as a JPEG file

Settings and trimming
This circuit does not require any trimming.

Références
  • Randall Kirschman, Electronics, Jul.1980,
  • Jonathan Jacky, Electronics, Sept.1980,
  • Örley Gàbor, Electronic Design, Aug. 1980,

The DIY builders' gallery
Here are the photographs of the yusynth ADSR modules built by other synth geeks around the world.
Thank you  guys for sending me these nice photos.

   

Name : Czaba ZVEKAN
Modular project :
Location : Basel, Switzerland
Website :  		Name : Etaoin
Modular project : Casia MS01
Location : Utrecht, Netherlands
Website :www.casia.org/modular
Name : Vins&Steph
Modular project : Xarolium
Location : France
Website :www.myspace.com/xarolium



Name : Jordi
Pseudo : vcfool
 Modular project :
Location :
Website :



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